1. Technical Field
Embodiments as disclosed herein relate to a semiconductor apparatus, and more particularly, to a 3D (three-dimensional) semiconductor apparatus using through-vias.
2. Related Art
In order to improve the degree of integration of a semiconductor apparatus, a 3D (three-dimensional) semiconductor apparatus, in which a plurality of chips are stacked and packaged to increase the degree of integration, has been developed. In the 3D semiconductor apparatus, since two or more chips are vertically stacked, a maximum degree of integration may be achieved in the same area.
Various methods may be applied to realize the 3D semiconductor apparatus. In one of the methods, a plurality of chips having the same structure are stacked and are then connected with one another using wires such as metal lines to operate as one semiconductor apparatus.
Recently, a TSV (through-silicon via) type semiconductor apparatus has been disclosed, in which through-silicon vias are formed to pass through a plurality of stacked chips so that all of the stacked chips are electrically connected with one another. In the TSV type semiconductor apparatus, because the through-silicon vias vertically pass through the respective chips to electrically connect them with one another, the area of a package may be efficiently reduced when compared to a semiconductor apparatus in which respective chips are connected with one another through peripheral wiring using wires.
Since each TSV is formed by filling a conductive material in a via hole which is defined through a dielectric substance, the TSV itself has capacitance. Due to this fact, even when a square wave signal is input, the signal output through the TSV exhibits a waveform that is approximately a triangular wave. While the TSV does not exhibit any noticeable problems when a signal with a wide pulse width is transmitted through the TSV, an unexpected fail may occur when a signal with a narrow pulse width is transmitted.
FIG. 1 is a view showing a configuration for transmitting a signal through a through-silicon via according to the prior art and the waveform of the signal transmitted through the configuration. A transmission unit 11 outputs input signals pulse_in1 and pulse_in2 with a first pulse width and a second pulse width, respectively, to a through-silicon via 12. According to the illustrated embodiment, the first pulse width corresponds to two cycles 2tCK of a clock signal and the second pulse width corresponds to one cycle 1tCK of the clock signal. Since the through-silicon via 12 has capacitance, it does not transmit the input signals pulse_in1 and pulse_in2 as they are and transmits them in triangular waveforms. A reception unit 13 receives and latches signals pulse_TSV1 and pulse_TSV2 which have passed through the through-silicon via 12, and generates output signals pulse_out1 and pulse_out2.
As shown in FIG. 1, even though the input signals pulse_in1 and pulse_in2 are square waves, the signals pulse_TSV1 and pulse_TSV2 output through the through-silicon via 12 are triangular waveforms. Although the input signal pulse_in1 with the first pulse width is changed into a triangular waveform while passing through the through-silicon via 12, since it has a sufficiently wide pulse width, a peak of the pulse_TSV1 waveform still reaches the voltage level VDD and maintains an average level of voltage level VDD and voltage level VSS that corresponds to a logic threshold of reception unit 13. Consequently, reception unit 13 is still able to properly receive and latch input signal pulse_in1. However, in the case of the input signal pulse_in2 with the second pulse width, since it has a narrow pulse width, it may not exceed a logic threshold of the reception unit 13 and therefore not be properly received and latched by reception unit 13. Moreover, even when it exceeds the logic threshold of the reception unit 13, because pulse_in2 has a narrow pulse width, a latched pulse width is also small, resulting in the input signal pulse_in2 is not being properly received by the reception unit 13.